1. Field of the Invention
The present invention relates to a photo mask correcting method for use in a manufacturing method of a semiconductor device using a double transfer method and to a manufacturing method of a semiconductor device using a corrected photo mask.
2. Description of the Related Art
In recent years, in the manufacture of a semiconductor memory device, continued progress has been made to obtain a higher integration density unit including elements and connection lines in a circuit and attain more microminiaturization of a pattern involved. In the manufacture of an RISC processor, etc., used as a CPU for an engineering work station (EWS) and personal computer (PC), a demand has been made for attaining a pattern whose transistor gate width is below 100 nm for the year 2002.
Recently, a method has been disclosed in which, in order to obtain more microminiaturized gate, a vary small gate is formed relative to a resist pattern (See paragraphs [0032] to [0049], FIGS. 1 to 6 of JPN PAT APPLN KOKAI PUBLICATION 2002-359352). Here, the method disclosed in this KOKAI PUBLICATION is called as a double transfer method.
First, a first resist pattern is formed using an alternating phase shift mask and, with this used as a mask, an underlying film is made slimmer. After the first pattern is removed, a resist is again coated on a surface and, by directing exposure light to a trimming mask, a second resist pattern is formed. After this, no slimming processing is applied to the underlying film or processing is done to a more slimming extent and, finally, a gate is formed. However, there is no disclosure in this KOKAI PUBLICATION as to how to very accurately form such an electrode of any desired dimensional width.